Commit 98de1333 authored by Bartmann, Peter's avatar Bartmann, Peter 😮
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#
# Vivado (TM) v2017.2 (64-bit)
#
# BuildVivadoProject.tcl: Tcl script for re-creating project 'led_example'
#
# Generated by Vivado on Tue Aug 15 14:40:55 +0200 2017
# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017
#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
# when this script was generated. In order to re-create the project, please source this
# file in the Vivado Tcl Shell.
#
# * Note that the runs in the created project will be configured the same way as the
# original project, however they will not be launched automatically. To regenerate the
# run results please launch the synthesis/implementation runs as needed.
#
#*****************************************************************************************
# NOTE: In order to use this script for source control purposes, please make sure that the
# following files are added to the source control system:-
#
# 1. This project restoration tcl script (BuildVivadoProject.tcl) that was generated.
#
# 2. The following source(s) files that were local or imported into the original project.
# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
#
# "./VivadoProject/led_example.srcs/sources_1/imports/hdl/system_wrapper.v"
#
# 3. The following remote source files that were added to the original project:-
#
# "./sources/bd/system/system.bd"
# "./sources/bd/system/hdl/system_wrapper.v"
# "./sources/constraints/redpitaya.xdc"
#
#*****************************************************************************************
# Set the reference directory for source file relative paths (by default the value is script directory path)
set origin_dir "."
# Use origin directory path location variable, if specified in the tcl shell
if { [info exists ::origin_dir_loc] } {
set origin_dir $::origin_dir_loc
}
variable script_file
set script_file "BuildVivadoProject.tcl"
# Help information for this script
proc help {} {
variable script_file
puts "\nDescription:"
puts "Recreate a Vivado project from this script. The created project will be"
puts "functionally equivalent to the original project for which this script was"
puts "generated. The script contains commands for creating a project, filesets,"
puts "runs, adding/importing sources and setting properties on various objects.\n"
puts "Syntax:"
puts "$script_file"
puts "$script_file -tclargs \[--origin_dir <path>\]"
puts "$script_file -tclargs \[--help\]\n"
puts "Usage:"
puts "Name Description"
puts "-------------------------------------------------------------------------"
puts "\[--origin_dir <path>\] Determine source file paths wrt this path. Default"
puts " origin_dir path value is \".\", otherwise, the value"
puts " that was set with the \"-paths_relative_to\" switch"
puts " when this script was generated.\n"
puts "\[--help\] Print help information for this script"
puts "-------------------------------------------------------------------------\n"
exit 0
}
if { $::argc > 0 } {
for {set i 0} {$i < [llength $::argc]} {incr i} {
set option [string trim [lindex $::argv $i]]
switch -regexp -- $option {
"--origin_dir" { incr i; set origin_dir [lindex $::argv $i] }
"--help" { help }
default {
if { [regexp {^-} $option] } {
puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
return 1
}
}
}
}
}
# Set the directory path for the original project from where this script was exported
set orig_proj_dir "[file normalize "$origin_dir/../led_example"]"
# Create project
create_project led_example ./VivadoProject -part xc7z010clg400-1
# Set the directory path for the new project
set proj_dir [get_property directory [current_project]]
# Reconstruct message rules
# None
# Set project properties
set obj [get_projects led_example]
set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
set_property -name "ip_cache_permissions" -value "read write" -objects $obj
set_property -name "ip_output_repo" -value "$proj_dir/led_example.cache/ip" -objects $obj
set_property -name "part" -value "xc7z010clg400-1" -objects $obj
set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
set_property -name "simulator_language" -value "Mixed" -objects $obj
set_property -name "xpm_libraries" -value "XPM_CDC" -objects $obj
set_property -name "xsim.array_display_limit" -value "64" -objects $obj
# Create 'sources_1' fileset (if not found)
if {[string equal [get_filesets -quiet sources_1] ""]} {
create_fileset -srcset sources_1
}
# Set 'sources_1' fileset object
set obj [get_filesets sources_1]
set files [list \
"[file normalize "$origin_dir/../led_example/sources/bd/system/system.bd"]"\
"[file normalize "$origin_dir/../led_example/sources/bd/system/hdl/system_wrapper.v"]"\
]
add_files -norecurse -fileset $obj $files
# Set 'sources_1' fileset file properties for remote files
# None
# Set 'sources_1' fileset file properties for local files
# None
# Set 'sources_1' fileset properties
set obj [get_filesets sources_1]
set_property -name "top" -value "system_wrapper" -objects $obj
# Create 'constrs_1' fileset (if not found)
if {[string equal [get_filesets -quiet constrs_1] ""]} {
create_fileset -constrset constrs_1
}
# Set 'constrs_1' fileset object
set obj [get_filesets constrs_1]
# Add/Import constrs file and set constrs file properties
set file "[file normalize "$origin_dir/../led_example/sources/constraints/redpitaya.xdc"]"
set file_added [add_files -norecurse -fileset $obj $file]
set file "$origin_dir/../led_example/sources/constraints/redpitaya.xdc"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
set_property -name "file_type" -value "XDC" -objects $file_obj
# Set 'constrs_1' fileset properties
set obj [get_filesets constrs_1]
set_property -name "target_constrs_file" -value "$orig_proj_dir/sources/constraints/redpitaya.xdc" -objects $obj
# Create 'sim_1' fileset (if not found)
if {[string equal [get_filesets -quiet sim_1] ""]} {
create_fileset -simset sim_1
}
# Set 'sim_1' fileset object
set obj [get_filesets sim_1]
# Empty (no sources present)
# Set 'sim_1' fileset properties
set obj [get_filesets sim_1]
set_property -name "top" -value "system_wrapper" -objects $obj
# Create 'synth_1' run (if not found)
if {[string equal [get_runs -quiet synth_1] ""]} {
create_run -name synth_1 -part xc7z010clg400-1 -flow {Vivado Synthesis 2017} -strategy "Vivado Synthesis Defaults" -constrset constrs_1
} else {
set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
set_property flow "Vivado Synthesis 2017" [get_runs synth_1]
}
set obj [get_runs synth_1]
set_property -name "part" -value "xc7z010clg400-1" -objects $obj
# set the current synth run
current_run -synthesis [get_runs synth_1]
# Create 'impl_1' run (if not found)
if {[string equal [get_runs -quiet impl_1] ""]} {
create_run -name impl_1 -part xc7z010clg400-1 -flow {Vivado Implementation 2017} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1
} else {
set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
set_property flow "Vivado Implementation 2017" [get_runs impl_1]
}
set obj [get_runs impl_1]
set_property -name "part" -value "xc7z010clg400-1" -objects $obj
set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
# set the current impl run
current_run -implementation [get_runs impl_1]
puts "INFO: Project created:led_example"
# How To ...
## ... Build Vivado Project
Follow the following steps:
- open Vivado
- in TCL console:
-- enter _pwd_ to check current folder
-- change folder with _cd_ command to working folder
-- execute tcl-script to create Vivado project: _source ./BuildVivadoProject_
Once executed the tcl script creates the overall Vivado project structure including the zynq processing system. The standalone application will not be created in this step.
If you are further interested in configuring the Zynq and it's periphals simply click on _Open Block Design_ in the _Project Manager_. The design includes the Zynq, the AXI interface and the GPIOs which are passed through the FPGA to the LEDs.
## ... Generate Bit File and Export Hardware
To generate the bit file simply double click on _Generate Bitstream_ the left side panel. This procedure may take some time.
Before changing from Vivado to the SDK (Eclipse based) one has to export the hardware information. This can be done over the top menu _File_ -> _Export_ -> _Export Hardware..._. In the following window select **include bitstream**, leave the **default folder** untouched and click on _OK_.
## ... Open SDK and Creating Projects
Now the SDK is prepared. The environment can be open over _File_ -> _Launch SDK_. Leave the **default setting** and click on _OK_. Eclipse with the Vivado SDK overlay will start.
You now have a dafault project available. This project contains the hardware information you have exported in advanced. In the following steps you four projects:
- Application project
- Board Supported Package (BSP) project for the application (will be created automatically)
- Application project for the First Stage Bootloader (FSBL)
- BSP project for the FSBL
To create a project select _File_ -> _New_ -> _Application Project_
### Application Project
In the opened window do the following steps:
- assign a freely chosen name for your application
- select _OS Platform_ **standalone**
- _Target Hardware_ is the _Hardware Platform_ **system_wrapper_hw_platform_0** and _Processor_ **ps7_cortexa9_0**
- By default a new board supported package will be created
Click on _Next>_ and select the **Hello World** template before _Finish_ the creation.
### FSBL Project
Apply all steps a second time but this time select the template **Zynq FSBL**
## Create Application and Bootimage
In the helloworld-template you have the _helloworld.c_ The source is located in ./VivadoProject/led_example.sdk/_application\_name_/src. Replace the helloworld.c in the project location with the one provided in ./sources/sdk/. Afterwards rebuild the application projects.
To build the bootimage:
- select the FSBL project
- Click in the top menu on _Xilinx Tools_ -> _Create Boot Image_
- In the opened window apply following settings:
-- Architecture: Zynq
-- Create new BIF file
-- Output BIF file path: ./VivadoProject/led_example.sdk/_fsbl\-application\_name_/bootimage/_fsbl\-application\_name_.bif
-- Output Path: ./VivadoProject/led_example.sdk/_fsbl\-application\_name_/bootimage/BOOT.bin
-- Boot image partition: (as described below)
- _Create Image_
### Boot image partitions
The first boot partition has to be the bootloader (the FSBL project). If it is not already in the list, you can add it manually by clicking on _Add_. You have to select application file ./VivadoProject/led_example.sdk/_fsbl\-application\_name_/Debug/_fsbl\-application\_name_.elf. Make sure that _Partition type_ **bootloader** is selected.
The remaining two partitions has to be
a) the FPGA bit file: ./VivadoProject/led_example.sdk/system_wrapper_hw_platform_0/system_wrapper.bit
b) the application: ./VivadoProject/led_example.sdk/_application\_name_/Debug/_application\_name_.elf
These partitions are of type **datafile**.
Once every boot partion is added into the list, one can _Create Image_.
## Run the Application
The output file ./VivadoProject/led_example.sdk/_fsbl\-application\_name_/bootimage/BOOT.bin can be copied into the root dir of a micro SD card. Insert this SD card into the RedPitaya and power on the device.
Once loaded you should see that the LEDs 0, 2, 4 and 6 are on and the LEDs 1, 3, 5 and 7 are switched off. This is the default state. You have access to the application using a serial terminal. Use baud rate of 115200, 8 data bits and 1 stop bit.
With each input to the console, the bit pattern on 0-7 inverts. If you enter '0' to the terminal you terminate the application.
\ No newline at end of file
//Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
//Date : Mon Aug 14 16:13:06 2017
//Host : PC0-DUE running 64-bit major release (build 9200)
//Command : generate_target system_wrapper.bd
//Design : system_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module system_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
leds_tri_io);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
inout [7:0]leds_tri_io;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
wire [0:0]leds_tri_i_0;
wire [1:1]leds_tri_i_1;
wire [2:2]leds_tri_i_2;
wire [3:3]leds_tri_i_3;
wire [4:4]leds_tri_i_4;
wire [5:5]leds_tri_i_5;
wire [6:6]leds_tri_i_6;
wire [7:7]leds_tri_i_7;
wire [0:0]leds_tri_io_0;
wire [1:1]leds_tri_io_1;
wire [2:2]leds_tri_io_2;
wire [3:3]leds_tri_io_3;
wire [4:4]leds_tri_io_4;
wire [5:5]leds_tri_io_5;
wire [6:6]leds_tri_io_6;
wire [7:7]leds_tri_io_7;
wire [0:0]leds_tri_o_0;
wire [1:1]leds_tri_o_1;
wire [2:2]leds_tri_o_2;
wire [3:3]leds_tri_o_3;
wire [4:4]leds_tri_o_4;
wire [5:5]leds_tri_o_5;
wire [6:6]leds_tri_o_6;
wire [7:7]leds_tri_o_7;
wire [0:0]leds_tri_t_0;
wire [1:1]leds_tri_t_1;
wire [2:2]leds_tri_t_2;
wire [3:3]leds_tri_t_3;
wire [4:4]leds_tri_t_4;
wire [5:5]leds_tri_t_5;
wire [6:6]leds_tri_t_6;
wire [7:7]leds_tri_t_7;
IOBUF leds_tri_iobuf_0
(.I(leds_tri_o_0),
.IO(leds_tri_io[0]),
.O(leds_tri_i_0),
.T(leds_tri_t_0));
IOBUF leds_tri_iobuf_1
(.I(leds_tri_o_1),
.IO(leds_tri_io[1]),
.O(leds_tri_i_1),
.T(leds_tri_t_1));
IOBUF leds_tri_iobuf_2
(.I(leds_tri_o_2),
.IO(leds_tri_io[2]),
.O(leds_tri_i_2),
.T(leds_tri_t_2));
IOBUF leds_tri_iobuf_3
(.I(leds_tri_o_3),
.IO(leds_tri_io[3]),
.O(leds_tri_i_3),
.T(leds_tri_t_3));
IOBUF leds_tri_iobuf_4
(.I(leds_tri_o_4),
.IO(leds_tri_io[4]),
.O(leds_tri_i_4),
.T(leds_tri_t_4));
IOBUF leds_tri_iobuf_5
(.I(leds_tri_o_5),
.IO(leds_tri_io[5]),
.O(leds_tri_i_5),
.T(leds_tri_t_5));
IOBUF leds_tri_iobuf_6
(.I(leds_tri_o_6),
.IO(leds_tri_io[6]),
.O(leds_tri_i_6),
.T(leds_tri_t_6));
IOBUF leds_tri_iobuf_7
(.I(leds_tri_o_7),
.IO(leds_tri_io[7]),
.O(leds_tri_i_7),
.T(leds_tri_t_7));
system system_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.leds_tri_i({leds_tri_i_7,leds_tri_i_6,leds_tri_i_5,leds_tri_i_4,leds_tri_i_3,leds_tri_i_2,leds_tri_i_1,leds_tri_i_0}),
.leds_tri_o({leds_tri_o_7,leds_tri_o_6,leds_tri_o_5,leds_tri_o_4,leds_tri_o_3,leds_tri_o_2,leds_tri_o_1,leds_tri_o_0}),
.leds_tri_t({leds_tri_t_7,leds_tri_t_6,leds_tri_t_5,leds_tri_t_4,leds_tri_t_3,leds_tri_t_2,leds_tri_t_1,leds_tri_t_0}));
endmodule
This diff is collapsed.
set_property PACKAGE_PIN F16 [get_ports {leds_tri_io[0]}]
set_property PACKAGE_PIN F17 [get_ports {leds_tri_io[1]}]
set_property PACKAGE_PIN G15 [get_ports {leds_tri_io[2]}]
set_property PACKAGE_PIN H15 [get_ports {leds_tri_io[3]}]
set_property PACKAGE_PIN K14 [get_ports {leds_tri_io[4]}]
set_property PACKAGE_PIN G14 [get_ports {leds_tri_io[5]}]
set_property PACKAGE_PIN J15 [get_ports {leds_tri_io[6]}]
set_property PACKAGE_PIN J14 [get_ports {leds_tri_io[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {leds_tri_io[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {leds_tri_io[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {leds_tri_io[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {leds_tri_io[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {leds_tri_io[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {leds_tri_io[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {leds_tri_io[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {leds_tri_io[0]}]
/******************************************************************************
*
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*
* helloworld.c: simple test application
*
* This application configures UART 16550 to baud rate 9600.
* PS7 UART (Zynq) is not initialized by this application, since
* bootrom/bsp configures it to baud rate 115200
*
* ------------------------------------------------
* | UART TYPE BAUD RATE |
* ------------------------------------------------
* uartns550 9600
* uartlite Configurable only in HW design
* ps7_uart 115200 (configured by bootrom/bsp)
*/
#include <stdio.h>
#include "platform.h"
#include "xgpio.h"
#include "xstatus.h"
#include "xil_printf.h"
#define XGPIO_DEVICE_ID XPAR_AXI_GPIO_0_DEVICE_ID
#define LED_CHANNEL 1
XGpio Gpio;
int main()
{
char c = 0x00;
int XGPio_Status;
init_platform();
print("Hello World\n\r");
XGPio_Status = XGpio_Initialize(&Gpio,XGPIO_DEVICE_ID);
if (XGPio_Status != XST_SUCCESS) {
return XST_FAILURE;
}
XGpio_SetDataDirection(&Gpio,LED_CHANNEL, 0x0); //set first channel tristate buffer to output
while (1) {
xil_printf("Press '0' to exit or anything to invert LEDs:\r\n");
c = inbyte();
if (c== '0') break;
u32 current_val = XGpio_DiscreteRead(&Gpio,LED_CHANNEL);
XGpio_DiscreteWrite(&Gpio,LED_CHANNEL,~current_val);
print("LEDs inverted\n\r");
}
print("Main program ended.\n\r");
cleanup_platform();
return 0;
}
#
# $Id: red_pitaya.xdc 961 2014-01-21 11:40:39Z matej.oblak $
#
# @brief Red Pitaya location constraints.
#
# @Author Matej Oblak
#
# (c) Red Pitaya http://www.redpitaya.com
#
############################################################################
# IO constraints #
############################################################################
### ADC
# ADC A data
set_property IOSTANDARD LVCMOS18 [get_ports {adc_dat_a_i[*]}]
set_property IOB TRUE [get_ports {adc_dat_a_i[*]}]
#set_property PACKAGE_PIN V17 [get_ports {adc_dat_a_i[0]}]
#set_property PACKAGE_PIN U17 [get_ports {adc_dat_a_i[1]}]
set_property PACKAGE_PIN Y17 [get_ports {adc_dat_a_i[2]}]
set_property PACKAGE_PIN W16 [get_ports {adc_dat_a_i[3]}]
set_property PACKAGE_PIN Y16 [get_ports {adc_dat_a_i[4]}]
set_property PACKAGE_PIN W15 [get_ports {adc_dat_a_i[5]}]
set_property PACKAGE_PIN W14 [get_ports {adc_dat_a_i[6]}]
set_property PACKAGE_PIN Y14 [get_ports {adc_dat_a_i[7]}]
set_property PACKAGE_PIN W13 [get_ports {adc_dat_a_i[8]}]
set_property PACKAGE_PIN V12 [get_ports {adc_dat_a_i[9]}]
set_property PACKAGE_PIN V13 [get_ports {adc_dat_a_i[10]}]
set_property PACKAGE_PIN T14 [get_ports {adc_dat_a_i[11]}]
set_property PACKAGE_PIN T15 [get_ports {adc_dat_a_i[12]}]
set_property PACKAGE_PIN V15 [get_ports {adc_dat_a_i[13]}]
set_property PACKAGE_PIN T16 [get_ports {adc_dat_a_i[14]}]
set_property PACKAGE_PIN V16 [get_ports {adc_dat_a_i[15]}]
# ADC B data
set_property IOSTANDARD LVCMOS18 [get_ports {adc_dat_b_i[*]}]
set_property IOB TRUE [get_ports {adc_dat_b_i[*]}]
#set_property PACKAGE_PIN T17 [get_ports {adc_dat_b_i[0]}]
#set_property PACKAGE_PIN R16 [get_ports {adc_dat_b_i[1]}]
set_property PACKAGE_PIN R18 [get_ports {adc_dat_b_i[2]}]
set_property PACKAGE_PIN P16 [get_ports {adc_dat_b_i[3]}]
set_property PACKAGE_PIN P18 [get_ports {adc_dat_b_i[4]}]
set_property PACKAGE_PIN N17 [get_ports {adc_dat_b_i[5]}]
set_property PACKAGE_PIN R19 [get_ports {adc_dat_b_i[6]}]
set_property PACKAGE_PIN T20 [get_ports {adc_dat_b_i[7]}]
set_property PACKAGE_PIN T19 [get_ports {adc_dat_b_i[8]}]
set_property PACKAGE_PIN U20 [get_ports {adc_dat_b_i[9]}]
set_property PACKAGE_PIN V20 [get_ports {adc_dat_b_i[10]}]
set_property PACKAGE_PIN W20 [get_ports {adc_dat_b_i[11]}]
set_property PACKAGE_PIN W19 [get_ports {adc_dat_b_i[12]}]
set_property PACKAGE_PIN Y19 [get_ports {adc_dat_b_i[13]}]