Commit df9f0f6e authored by Bartmann, Peter's avatar Bartmann, Peter 😮
Browse files

add verilog template

parent 9c598de5
# Copyright (C) 2020 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
# Quartus Prime Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition
# File: D:\UserData\Bartmann\Workspaces\Git\EmbSys_RISCV\platform\cyc1000\cyc1000_assignments.csv
# Generated on: Fri Mar 19 10:23:00 2021
Status,From,To,Assignment Name,Value,Enabled,Entity,Comment,Tag
Ok,,CLK12M_i,Location,PIN_M2,Yes,,,
Ok,,CLKx_i,Location,PIN_E15,Yes,,,
Ok,,LED_o[7],Location,PIN_N3,Yes,,,
Ok,,LED_o[6],Location,PIN_N5,Yes,,,
Ok,,LED_o[5],Location,PIN_R4,Yes,,,
Ok,,LED_o[4],Location,PIN_T2,Yes,,,
Ok,,LED_o[3],Location,PIN_R3,Yes,,,
Ok,,LED_o[2],Location,PIN_T3,Yes,,,
Ok,,LED_o[1],Location,PIN_T4,Yes,,,
Ok,,LED_o[0],Location,PIN_M6,Yes,,,
Ok,,USER_BTN_i,Location,PIN_N6,Yes,,,
Ok,,SEN_INT_i[0],Location,PIN_B1,Yes,,,
Ok,,SEN_INT_i[1],Location,PIN_C2,Yes,,,
Ok,,SEN_SDI_o,Location,PIN_G2,Yes,,,
Ok,,SEN_SDO_i,Location,PIN_G1,Yes,,,
Ok,,SEN_SPC_o,Location,PIN_F3,Yes,,,
Ok,,SEN_CS_o,Location,PIN_D1,Yes,,,
Ok,,SDRAM_ADDR_o[0],Location,PIN_A3,Yes,,,
Ok,,SDRAM_ADDR_o[1],Location,PIN_B5,Yes,,,
Ok,,SDRAM_ADDR_o[2],Location,PIN_B4,Yes,,,
Ok,,SDRAM_ADDR_o[3],Location,PIN_B3,Yes,,,
Ok,,SDRAM_ADDR_o[4],Location,PIN_C3,Yes,,,
Ok,,SDRAM_ADDR_o[5],Location,PIN_D3,Yes,,,
Ok,,SDRAM_ADDR_o[6],Location,PIN_E6,Yes,,,
Ok,,SDRAM_ADDR_o[7],Location,PIN_E7,Yes,,,
Ok,,SDRAM_ADDR_o[8],Location,PIN_D6,Yes,,,
Ok,,SDRAM_ADDR_o[9],Location,PIN_D8,Yes,,,
Ok,,SDRAM_ADDR_o[10],Location,PIN_A5,Yes,,,
Ok,,SDRAM_ADDR_o[11],Location,PIN_E8,Yes,,,
Ok,,SDRAM_ADDR_o[12],Location,PIN_A2,Yes,,,
Ok,,SDRAM_ADDR_o[13],Location,PIN_C6,Yes,,,
Ok,,SDRAM_BA_o[0],Location,PIN_A4,Yes,,,
Ok,,SDRAM_BA_o[1],Location,PIN_B6,Yes,,,
Ok,,SDRAM_nRAS_o,Location,PIN_B7,Yes,,,
Ok,,SDRAM_nCAS_o,Location,PIN_C8,Yes,,,
Ok,,SDRAM_nCS_o,Location,PIN_A6,Yes,,,
Ok,,SDRAM_nWE_o,Location,PIN_A7,Yes,,,
Ok,,SDRAM_CKE_o,Location,PIN_F8,Yes,,,
Ok,,SDRAM_CLK_o,Location,PIN_B14,Yes,,,
Ok,,SDRAM_DQM_o[0],Location,PIN_B13,Yes,,,
Ok,,SDRAM_DQM_o[1],Location,PIN_D12,Yes,,,
Ok,,SDRAM_DQ_io[15],Location,PIN_A14,Yes,,,
Ok,,SDRAM_DQ_io[14],Location,PIN_C14,Yes,,,
Ok,,SDRAM_DQ_io[13],Location,PIN_F9,Yes,,,
Ok,,SDRAM_DQ_io[12],Location,PIN_D14,Yes,,,
Ok,,SDRAM_DQ_io[11],Location,PIN_E9,Yes,,,
Ok,,SDRAM_DQ_io[10],Location,PIN_A15,Yes,,,
Ok,,SDRAM_DQ_io[9],Location,PIN_E11,Yes,,,
Ok,,SDRAM_DQ_io[8],Location,PIN_C11,Yes,,,
Ok,,SDRAM_DQ_io[7],Location,PIN_C9,Yes,,,
Ok,,SDRAM_DQ_io[6],Location,PIN_B12,Yes,,,
Ok,,SDRAM_DQ_io[5],Location,PIN_D9,Yes,,,
Ok,,SDRAM_DQ_io[4],Location,PIN_A12,Yes,,,
Ok,,SDRAM_DQ_io[3],Location,PIN_A11,Yes,,,
Ok,,SDRAM_DQ_io[2],Location,PIN_B11,Yes,,,
Ok,,SDRAM_DQ_io[1],Location,PIN_A10,Yes,,,
Ok,,SDRAM_DQ_io[0],Location,PIN_B10,Yes,,,
Ok,,MKR_AREF_io,Location,PIN_P11,Yes,,,
Ok,,MKR_AIN_io[0],Location,PIN_R12,Yes,,,
Ok,,MKR_AIN_io[1],Location,PIN_T13,Yes,,,
Ok,,MKR_AIN_io[2],Location,PIN_R13,Yes,,,
Ok,,MKR_AIN_io[3],Location,PIN_T14,Yes,,,
Ok,,MKR_AIN_io[4],Location,PIN_P14,Yes,,,
Ok,,MKR_AIN_io[5],Location,PIN_R14,Yes,,,
Ok,,MKR_AIN_io[6],Location,PIN_T15,Yes,,,
Ok,,MKR_D_io[0],Location,PIN_N16,Yes,,,
Ok,,MKR_D_io[1],Location,PIN_L15,Yes,,,
Ok,,MKR_D_io[2],Location,PIN_L16,Yes,,,
Ok,,MKR_D_io[3],Location,PIN_K15,Yes,,,
Ok,,MKR_D_io[4],Location,PIN_K16,Yes,,,
Ok,,MKR_D_io[5],Location,PIN_J14,Yes,,,
Ok,,MKR_D_io[6],Location,PIN_N2,Yes,,,
Ok,,MKR_D_io[7],Location,PIN_N1,Yes,,,
Ok,,MKR_D_io[8],Location,PIN_P2,Yes,,,
Ok,,MKR_D_io[9],Location,PIN_J1,Yes,,,
Ok,,MKR_D_io[10],Location,PIN_J2,Yes,,,
Ok,,MKR_D_io[11],Location,PIN_K2,Yes,,,
Ok,,MKR_D_io[12],Location,PIN_L2,Yes,,,
Ok,,MKR_D_io[13],Location,PIN_P1,Yes,,,
Ok,,MKR_D_io[14],Location,PIN_R1,Yes,,,
Ok,,MKR_D_R_io[11],Location,PIN_K1,Yes,,,
Ok,,MKR_D_R_io[12],Location,PIN_L1,Yes,,,
Ok,,PMOD_io[0],Location,PIN_F14,Yes,,,
Ok,,PMOD_io[1],Location,PIN_F15,Yes,,,
Ok,,PMOD_io[2],Location,PIN_F16,Yes,,,
Ok,,PMOD_io[3],Location,PIN_D16,Yes,,,
Ok,,PMOD_io[4],Location,PIN_D15,Yes,,,
Ok,,PMOD_io[5],Location,PIN_C15,Yes,,,
Ok,,PMOD_io[6],Location,PIN_B16,Yes,,,
Ok,,PMOD_io[7],Location,PIN_C16,Yes,,,
Ok,,USR_AIN_io[0],Location,PIN_T12,Yes,,,
Ok,,USR_AIN_io[1],Location,PIN_R11,Yes,,,
Ok,,UART_BDBUS_io[0],Location,PIN_R7,Yes,,,
Ok,,UART_BDBUS_io[1],Location,PIN_T7,Yes,,,
Ok,,UART_BDBUS_io[2],Location,PIN_R6,Yes,,,
Ok,,UART_BDBUS_io[3],Location,PIN_T6,Yes,,,
Ok,,UART_BDBUS_io[4],Location,PIN_R5,Yes,,,
Ok,,UART_BDBUS_io[5],Location,PIN_T5,Yes,,,
Ok,,UART_BDBUS_io,I/O Standard,3.3-V LVTTL,Yes,cyc1000_top,,
Ok,,USER_BTN_i,I/O Standard,3.3-V LVTTL,Yes,cyc1000_top,,
Ok,,LED_o,I/O Standard,3.3-V LVTTL,Yes,cyc1000_top,,
Ok,,USR_AIN_io,I/O Standard,3.3-V LVTTL,Yes,cyc1000_top,,
Ok,,PMOD_io,I/O Standard,3.3-V LVTTL,Yes,cyc1000_top,,
Ok,,MKR_*,I/O Standard,3.3-V LVTTL,Yes,cyc1000_top,,
Ok,,SEN_*,I/O Standard,3.3-V LVTTL,Yes,cyc1000_top,,
Ok,,SDRAM_*,I/O Standard,3.3-V LVTTL,Yes,cyc1000_top,,
Ok,,CLK*,I/O Standard,3.3-V LVTTL,Yes,cyc1000_top,,
,<<new>>,<<new>>,<<new>>,,,,,
//////////////////////////////////////////////////////////////////////////////
//
// file cyc1000_top.v
// author Peter Bartmann <peter.bartmann@th-luebeck.de>
// data 2021-03-19
//
//////////////////////////////////////////////////////////////////////////////
module cyc1000_top (
// Clock
CLK12M_i,
CLKx_i,
// SDRAM
SDRAM_CLK_o,
SDRAM_CKE_o,
SDRAM_nCS_o,
SDRAM_nRAS_o,
SDRAM_nCAS_o,
SDRAM_nWE_o,
SDRAM_ADDR_o,
SDRAM_BA_o,
SDRAM_DQ_io,
SDRAM_DQM_o,
// accelerometer connections
SEN_INT_i,
SEN_SDI_o,
SEN_SDO_i,
SEN_SPC_o,
SEN_CS_o,
// arduino MKR connectors
MKR_AREF_io,
MKR_AIN_io,
MKR_D_io,
MKR_D_R_io,
// PMOD connector
PMOD_io,
// additional user io
USR_AIN_io,
// UART with FT2232H (U3)
UART_BDBUS_io,
// push buttons
USER_BTN_i,
// LEDs
LED_o
);
input CLK12M_i; // (U7) external clock tree: shared with FT2232H (U3)
input CLKx_i; // (U6) optional oscillator
output SDRAM_CLK_o;
output SDRAM_CKE_o; // clock enable
output SDRAM_nCS_o; // chip select
output SDRAM_nRAS_o; // row address strobe
output SDRAM_nCAS_o; // column address strobe
output SDRAM_nWE_o; // write enable
output [13:0] SDRAM_ADDR_o;
output [ 1:0] SDRAM_BA_o;
inout [15:0] SDRAM_DQ_io;
output [ 1:0] SDRAM_DQM_o;
input [1:0] SEN_INT_i;
output SEN_SDI_o; // SPI MOSI
input SEN_SDO_i; // SPI MISO
output SEN_SPC_o; // SPI clock
output SEN_CS_o; // SPI chip select
inout MKR_AREF_io;
inout [ 6:0] MKR_AIN_io;
inout [14:0] MKR_D_io;
inout [12:0] MKR_D_R_io; // shared with D_io(12 downto 11) but with resistor
inout [7:0] PMOD_io;
inout [1:0] USR_AIN_io;
inout [5:0] UART_BDBUS_io;
input USER_BTN_i;
output [7:0] LED_o;
// start of rtl
endmodule
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