Commit aae7c75c authored by Bartmann, Peter's avatar Bartmann, Peter 😮
Browse files

initial commit

parents
[submodule "sdram"]
path = sdram
url = https://github.com/MinatsuT/CYC1000_SDRAM
Get started with the CYC1000 development kit by [trenz electronic](https://www.trenz-electronic.de/de/).
This repository is structured as follows:
- [documentation](./documentation): Documentation available for the CYC1000 development kit
- [tools](./tools): driver for the Arrow USB Blaster
- [blinky](./blinky): example Quartus Prime project for the CYC1000. You can have blinky LEDs, yeah :D
- [sdram](./sdram): example project using the SDRAM by [MinatsuT](https://github.com/MinatsuT/)
\ No newline at end of file
This is just the example project as described in the [User's Guide](../documentation/CYC1000 User Guide.pdf)!
Have fun with it. It's pretty neat, imo :)
\ No newline at end of file
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "graphic" (version "1.4"))
(pin
(input)
(rect -8 112 160 128)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "CLK12" (rect 5 0 39 12)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "GND" (rect 128 7 149 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 128 360 296 376)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "USER_BTN" (rect 5 0 57 17)(font "Intel Clear" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "GND" (rect 128 7 149 17)(font "Arial" (font_size 6)))
)
(pin
(output)
(rect 560 280 736 296)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "LED[7..0]" (rect 90 0 137 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
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(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
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)
(symbol
(rect 304 240 448 320)
(text "counter_mux" (rect 36 0 124 16)(font "Arial" (font_size 10)))
(text "inst" (rect 8 64 25 76)(font "Arial" ))
(port
(pt 0 40)
(input)
(text "data1x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
(text "data1x[7..0]" (rect 4 26 71 40)(font "Arial" (font_size 8)))
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(port
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(input)
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(line (pt 0 56)(pt 64 56)(line_width 3))
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(port
(pt 72 80)
(input)
(text "sel" (rect 0 0 14 16)(font "Arial" (font_size 8))(vertical))
(text "sel" (rect 65 51 79 67)(font "Arial" (font_size 8))(vertical))
(line (pt 72 80)(pt 72 68))
)
(port
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(output)
(text "result[7..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
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(line (pt 144 48)(pt 80 48)(line_width 3))
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(drawing
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(symbol
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(text "simple_counter" (rect 29 0 132 16)(font "Arial" (font_size 10)))
(text "inst2" (rect 8 48 30 65)(font "Intel Clear" ))
(port
(pt 0 32)
(input)
(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
(text "clock" (rect 26 25 55 39)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32))
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(port
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(output)
(text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
(text "q[31..0]" (rect 89 33 131 47)(font "Arial" (font_size 8)))
(line (pt 144 40)(pt 128 40)(line_width 3))
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(drawing
(text "up counter" (rect 84 22 135 34)(font "Arial" ))
(line (pt 16 16)(pt 16 48))
(line (pt 16 16)(pt 128 16))
(line (pt 16 48)(pt 128 48))
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(symbol
(rect 208 56 448 208)
(text "pll" (rect 114 0 129 16)(font "Arial" (font_size 10)))
(text "inst3" (rect 8 136 30 153)(font "Intel Clear" ))
(port
(pt 0 64)
(input)
(text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
(text "inclk0" (rect 4 50 35 64)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 40 64))
)
(port
(pt 240 64)
(output)
(text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "c0" (rect 224 50 238 64)(font "Arial" (font_size 8)))
)
(drawing
(text "Cyclone 10 LP" (rect 155 136 228 148)(font "Arial" ))
(text "inclk0 frequency: 12.000 MHz" (rect 50 59 197 71)(font "Arial" ))
(text "Operation Mode: Normal" (rect 50 72 169 84)(font "Arial" ))
(text "Clk " (rect 51 93 71 105)(font "Arial" ))
(text "Ratio" (rect 72 93 97 105)(font "Arial" ))
(text "Ph (dg)" (rect 98 93 133 105)(font "Arial" ))
(text "DC (%)" (rect 132 93 168 105)(font "Arial" ))
(text "c0" (rect 54 107 65 119)(font "Arial" ))
(text "5/3" (rect 77 107 92 119)(font "Arial" ))
(text "0.00" (rect 104 107 125 119)(font "Arial" ))
(text "50.00" (rect 136 107 163 119)(font "Arial" ))
(line (pt 0 0)(pt 241 0))
(line (pt 241 0)(pt 241 153))
(line (pt 0 153)(pt 241 153))
(line (pt 0 0)(pt 0 153))
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)
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(connector
(text "counter[24..31]" (rect 178 264 248 281)(font "Intel Clear" ))
(pt 304 280)
(pt 168 280)
(bus)
)
(connector
(text "counter[19..26]" (rect 178 280 248 297)(font "Intel Clear" ))
(pt 304 296)
(pt 168 296)
(bus)
)
(connector
(text "counter[31..0]" (rect 730 112 794 129)(font "Intel Clear" ))
(pt 720 128)
(pt 800 128)
(bus)
)
(connector
(pt 448 120)
(pt 576 120)
)
(connector
(pt 576 120)
(pt 584 120)
)
(connector
(pt 160 120)
(pt 208 120)
)
(connector
(pt 296 368)
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)
(connector
(pt 376 368)
(pt 376 320)
)
(connector
(pt 448 288)
(pt 560 288)
(bus)
)
(junction (pt 576 120))
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2020 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition
# Date created = 16:40:12 March 18, 2021
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "20.1"
DATE = "16:40:12 March 18, 2021"
# Revisions
PROJECT_REVISION = "blinky_top"
set_global_assignment -name FAMILY "Cyclone 10 LP"
set_global_assignment -name DEVICE 10CL025YU256C8G
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:40:12 MARCH 18, 2021"
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.0 Lite Edition"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
## PINOUT
##=======
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_location_assignment PIN_M2 -to CLK12
set_location_assignment PIN_N6 -to USER_BTN
set_location_assignment PIN_M6 -to LED[0]
set_location_assignment PIN_T4 -to LED[1]
set_location_assignment PIN_T3 -to LED[2]
set_location_assignment PIN_R3 -to LED[3]
set_location_assignment PIN_T2 -to LED[4]
set_location_assignment PIN_R4 -to LED[5]
set_location_assignment PIN_N5 -to LED[6]
set_location_assignment PIN_N3 -to LED[7]
## FILES
##======
set_global_assignment -name TOP_LEVEL_ENTITY blinky_top
set_global_assignment -name BDF_FILE blinky_top.bdf
set_global_assignment -name QIP_FILE pll.qip
set_global_assignment -name QIP_FILE simple_counter.qip
set_global_assignment -name QIP_FILE counter_mux.qip
set_global_assignment -name SDC_FILE blinky_top.sdc
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
## QUARTUS ADDITIONS
##==================
set_global_assignment -name ENABLE_OCT_DONE OFF
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
#create input clock which is 12MHz
create_clock -name CLK12 -period 83.333 [get_ports {CLK12}]
#derive PLL clocks
derive_pll_clocks
#derive clock uncertainty
derive_clock_uncertainty
#set false path
set_false_path -from [get_ports {USER_BTN}]
set_false_path -from * -to [get_ports {LED*}]
\ No newline at end of file
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.2"))
(symbol
(rect 0 0 144 80)
(text "counter_mux" (rect 36 0 124 16)(font "Arial" (font_size 10)))
(text "inst" (rect 8 64 25 76)(font "Arial" ))
(port
(pt 0 40)
(input)
(text "data1x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
(text "data1x[7..0]" (rect 4 26 59 39)(font "Arial" (font_size 8)))
(line (pt 0 40)(pt 64 40)(line_width 3))
)
(port
(pt 0 56)
(input)
(text "data0x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
(text "data0x[7..0]" (rect 4 42 59 55)(font "Arial" (font_size 8)))
(line (pt 0 56)(pt 64 56)(line_width 3))
)
(port
(pt 72 80)
(input)
(text "sel" (rect 0 0 14 16)(font "Arial" (font_size 8))(vertical))
(text "sel" (rect 65 51 78 63)(font "Arial" (font_size 8))(vertical))
(line (pt 72 80)(pt 72 68))
)
(port
(pt 144 48)
(output)
(text "result[7..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
(text "result[7..0]" (rect 90 34 139 47)(font "Arial" (font_size 8)))
(line (pt 144 48)(pt 80 48)(line_width 3))
)
(drawing
(line (pt 64 24)(pt 64 72))
(line (pt 64 24)(pt 80 32))
(line (pt 64 72)(pt 80 64))
(line (pt 80 32)(pt 80 64))
(line (pt 0 0)(pt 146 0))
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(line (pt 0 0)(pt 0 0))
(line (pt 0 0)(pt 0 0))
(line (pt 0 0)(pt 0 0))
(line (pt 0 0)(pt 0 0))
)
)
set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
set_global_assignment -name IP_TOOL_VERSION "20.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone 10 LP}"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "counter_mux.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "counter_mux.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "counter_mux.cmp"]
-- megafunction wizard: %LPM_MUX%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_MUX
-- ============================================================
-- File Name: counter_mux.vhd
-- Megafunction Name(s):
-- LPM_MUX
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 20.1.0 Build 711 06/05/2020 SJ Lite Edition
-- ************************************************************
--Copyright (C) 2020 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and any partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel FPGA IP License Agreement, or other applicable license
--agreement, including, without limitation, that your use is for
--the sole purpose of programming logic devices manufactured by
--Intel and sold by Intel or its authorized distributors. Please
--refer to the applicable agreement for further details, at
--https://fpgasoftware.intel.com/eula.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY counter_mux IS
PORT
(
data0x : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data1x : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
sel : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END counter_mux;
ARCHITECTURE SYN OF counter_mux IS
-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_2D (1 DOWNTO 0, 7 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
sub_wire2 <= data0x(7 DOWNTO 0);
sub_wire0 <= data1x(7 DOWNTO 0);
sub_wire1(1, 0) <= sub_wire0(0);
sub_wire1(1, 1) <= sub_wire0(1);
sub_wire1(1, 2) <= sub_wire0(2);
sub_wire1(1, 3) <= sub_wire0(3);
sub_wire1(1, 4) <= sub_wire0(4);
sub_wire1(1, 5) <= sub_wire0(5);
sub_wire1(1, 6) <= sub_wire0(6);
sub_wire1(1, 7) <= sub_wire0(7);
sub_wire1(0, 0) <= sub_wire2(0);
sub_wire1(0, 1) <= sub_wire2(1);
sub_wire1(0, 2) <= sub_wire2(2);
sub_wire1(0, 3) <= sub_wire2(3);
sub_wire1(0, 4) <= sub_wire2(4);
sub_wire1(0, 5) <= sub_wire2(5);
sub_wire1(0, 6) <= sub_wire2(6);
sub_wire1(0, 7) <= sub_wire2(7);
sub_wire3 <= sel;
sub_wire4(0) <= sub_wire3;
result <= sub_wire5(7 DOWNTO 0);
LPM_MUX_component : LPM_MUX
GENERIC MAP (
lpm_size => 2,
lpm_type => "LPM_MUX",
lpm_width => 8,
lpm_widths => 1
)
PORT MAP (
data => sub_wire1,
sel => sub_wire4,
result => sub_wire5
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
-- Retrieval info: USED_PORT: data0x 0 0 8 0 INPUT NODEFVAL "data0x[7..0]"
-- Retrieval info: USED_PORT: data1x 0 0 8 0 INPUT NODEFVAL "data1x[7..0]"
-- Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL "result[7..0]"
-- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL "sel"
-- Retrieval info: CONNECT: @data 1 0 8 0 data0x 0 0 8 0
-- Retrieval info: CONNECT: @data 1 1 8 0 data1x 0 0 8 0
-- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
-- Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL counter_mux.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL counter_mux.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL counter_mux.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL counter_mux.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL counter_mux_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
This diff is collapsed.
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.2"))
(symbol
(rect 0 0 240 152)
(text "pll" (rect 114 0 129 16)(font "Arial" (font_size 10)))
(text "inst" (rect 8 136 25 148)(font "Arial" ))
(port
(pt 0 64)
(input)
(text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
(text "inclk0" (rect 4 50 29 63)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 40 64))
)
(port
(pt 240 64)
(output)
(text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "c0" (rect 224 50 234 63)(font "Arial" (font_size 8)))
)
(drawing
(text "Cyclone 10 LP" (rect 155 136 370 283)(font "Arial" ))
(text "inclk0 frequency: 12.000 MHz" (rect 50 59 223 129)(font "Arial" ))
(text "Operation Mode: Normal" (rect 50 72 199 155)(font "Arial" ))
(text "Clk " (rect 51 93 116 197)(font "Arial" ))
(text "Ratio" (rect 72 93 164 197)(font "Arial" ))
(text "Ph (dg)" (rect 98 93 225 197)(font "Arial" ))
(text "DC (%)" (rect 132 93 294 197)(font "Arial" ))
(text "c0" (rect 54 107 116 225)(font "Arial" ))
(text "5/3" (rect 77 107 165 225)(font "Arial" ))
(text "0.00" (rect 104 107 224 225)(font "Arial" ))
(text "50.00" (rect 136 107 293 225)(font "Arial" ))
(line (pt 0 0)(pt 241 0))
(line (pt 241 0)(pt 241 153))
(line (pt 0 153)(pt 241 153))
(line (pt 0 0)(pt 0 153))
(line (pt 48 91)(pt 164 91))
(line (pt 48 104)(pt 164 104))
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