Commit 519bef31 authored by Bartmann, Peter's avatar Bartmann, Peter 😮
Browse files

add vhdl template for a new project

parent c66b6efc
......@@ -6,6 +6,7 @@ This repository is structured as follows:
- [examples](./examples): example projects ready to use
- [blinky](./examples/blinky): example Quartus Prime project for the CYC1000. You can have blinky LEDs, yeah :D
- [sdram](./examples/sdram): example project using the SDRAM by [MinatsuT](https://github.com/MinatsuT/)
- [templates](./templates): templates for top modules; useful to get start with your own project!
......
# Copyright (C) 2020 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
# Quartus Prime Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition
# File: D:\UserData\Bartmann\Workspaces\Git\EmbSys_RISCV\platform\cyc1000\cyc1000_assignments.csv
# Generated on: Fri Mar 19 10:23:00 2021
Status,From,To,Assignment Name,Value,Enabled,Entity,Comment,Tag
Ok,,CLK12M_i,Location,PIN_M2,Yes,,,
Ok,,CLKx_i,Location,PIN_E15,Yes,,,
Ok,,LED_o[7],Location,PIN_N3,Yes,,,
Ok,,LED_o[6],Location,PIN_N5,Yes,,,
Ok,,LED_o[5],Location,PIN_R4,Yes,,,
Ok,,LED_o[4],Location,PIN_T2,Yes,,,
Ok,,LED_o[3],Location,PIN_R3,Yes,,,
Ok,,LED_o[2],Location,PIN_T3,Yes,,,
Ok,,LED_o[1],Location,PIN_T4,Yes,,,
Ok,,LED_o[0],Location,PIN_M6,Yes,,,
Ok,,USER_BTN_i,Location,PIN_N6,Yes,,,
Ok,,SEN_INT_i[0],Location,PIN_B1,Yes,,,
Ok,,SEN_INT_i[1],Location,PIN_C2,Yes,,,
Ok,,SEN_SDI_o,Location,PIN_G2,Yes,,,
Ok,,SEN_SDO_i,Location,PIN_G1,Yes,,,
Ok,,SEN_SPC_o,Location,PIN_F3,Yes,,,
Ok,,SEN_CS_o,Location,PIN_D1,Yes,,,
Ok,,SDRAM_ADDR_o[0],Location,PIN_A3,Yes,,,
Ok,,SDRAM_ADDR_o[1],Location,PIN_B5,Yes,,,
Ok,,SDRAM_ADDR_o[2],Location,PIN_B4,Yes,,,
Ok,,SDRAM_ADDR_o[3],Location,PIN_B3,Yes,,,
Ok,,SDRAM_ADDR_o[4],Location,PIN_C3,Yes,,,
Ok,,SDRAM_ADDR_o[5],Location,PIN_D3,Yes,,,
Ok,,SDRAM_ADDR_o[6],Location,PIN_E6,Yes,,,
Ok,,SDRAM_ADDR_o[7],Location,PIN_E7,Yes,,,
Ok,,SDRAM_ADDR_o[8],Location,PIN_D6,Yes,,,
Ok,,SDRAM_ADDR_o[9],Location,PIN_D8,Yes,,,
Ok,,SDRAM_ADDR_o[10],Location,PIN_A5,Yes,,,
Ok,,SDRAM_ADDR_o[11],Location,PIN_E8,Yes,,,
Ok,,SDRAM_ADDR_o[12],Location,PIN_A2,Yes,,,
Ok,,SDRAM_ADDR_o[13],Location,PIN_C6,Yes,,,
Ok,,SDRAM_BA_o[0],Location,PIN_A4,Yes,,,
Ok,,SDRAM_BA_o[1],Location,PIN_B6,Yes,,,
Ok,,SDRAM_nRAS_o,Location,PIN_B7,Yes,,,
Ok,,SDRAM_nCAS_o,Location,PIN_C8,Yes,,,
Ok,,SDRAM_nCS_o,Location,PIN_A6,Yes,,,
Ok,,SDRAM_nWE_o,Location,PIN_A7,Yes,,,
Ok,,SDRAM_CKE_o,Location,PIN_F8,Yes,,,
Ok,,SDRAM_CLK_o,Location,PIN_B14,Yes,,,
Ok,,SDRAM_DQM_o[0],Location,PIN_B13,Yes,,,
Ok,,SDRAM_DQM_o[1],Location,PIN_D12,Yes,,,
Ok,,SDRAM_DQ_io[15],Location,PIN_A14,Yes,,,
Ok,,SDRAM_DQ_io[14],Location,PIN_C14,Yes,,,
Ok,,SDRAM_DQ_io[13],Location,PIN_F9,Yes,,,
Ok,,SDRAM_DQ_io[12],Location,PIN_D14,Yes,,,
Ok,,SDRAM_DQ_io[11],Location,PIN_E9,Yes,,,
Ok,,SDRAM_DQ_io[10],Location,PIN_A15,Yes,,,
Ok,,SDRAM_DQ_io[9],Location,PIN_E11,Yes,,,
Ok,,SDRAM_DQ_io[8],Location,PIN_C11,Yes,,,
Ok,,SDRAM_DQ_io[7],Location,PIN_C9,Yes,,,
Ok,,SDRAM_DQ_io[6],Location,PIN_B12,Yes,,,
Ok,,SDRAM_DQ_io[5],Location,PIN_D9,Yes,,,
Ok,,SDRAM_DQ_io[4],Location,PIN_A12,Yes,,,
Ok,,SDRAM_DQ_io[3],Location,PIN_A11,Yes,,,
Ok,,SDRAM_DQ_io[2],Location,PIN_B11,Yes,,,
Ok,,SDRAM_DQ_io[1],Location,PIN_A10,Yes,,,
Ok,,SDRAM_DQ_io[0],Location,PIN_B10,Yes,,,
Ok,,MKR_AREF_io,Location,PIN_P11,Yes,,,
Ok,,MKR_AIN_io[0],Location,PIN_R12,Yes,,,
Ok,,MKR_AIN_io[1],Location,PIN_T13,Yes,,,
Ok,,MKR_AIN_io[2],Location,PIN_R13,Yes,,,
Ok,,MKR_AIN_io[3],Location,PIN_T14,Yes,,,
Ok,,MKR_AIN_io[4],Location,PIN_P14,Yes,,,
Ok,,MKR_AIN_io[5],Location,PIN_R14,Yes,,,
Ok,,MKR_AIN_io[6],Location,PIN_T15,Yes,,,
Ok,,MKR_D_io[0],Location,PIN_N16,Yes,,,
Ok,,MKR_D_io[1],Location,PIN_L15,Yes,,,
Ok,,MKR_D_io[2],Location,PIN_L16,Yes,,,
Ok,,MKR_D_io[3],Location,PIN_K15,Yes,,,
Ok,,MKR_D_io[4],Location,PIN_K16,Yes,,,
Ok,,MKR_D_io[5],Location,PIN_J14,Yes,,,
Ok,,MKR_D_io[6],Location,PIN_N2,Yes,,,
Ok,,MKR_D_io[7],Location,PIN_N1,Yes,,,
Ok,,MKR_D_io[8],Location,PIN_P2,Yes,,,
Ok,,MKR_D_io[9],Location,PIN_J1,Yes,,,
Ok,,MKR_D_io[10],Location,PIN_J2,Yes,,,
Ok,,MKR_D_io[11],Location,PIN_K2,Yes,,,
Ok,,MKR_D_io[12],Location,PIN_L2,Yes,,,
Ok,,MKR_D_io[13],Location,PIN_P1,Yes,,,
Ok,,MKR_D_io[14],Location,PIN_R1,Yes,,,
Ok,,MKR_D_R_io[11],Location,PIN_K1,Yes,,,
Ok,,MKR_D_R_io[12],Location,PIN_L1,Yes,,,
Ok,,PMOD_io[0],Location,PIN_F14,Yes,,,
Ok,,PMOD_io[1],Location,PIN_F15,Yes,,,
Ok,,PMOD_io[2],Location,PIN_F16,Yes,,,
Ok,,PMOD_io[3],Location,PIN_D16,Yes,,,
Ok,,PMOD_io[4],Location,PIN_D15,Yes,,,
Ok,,PMOD_io[5],Location,PIN_C15,Yes,,,
Ok,,PMOD_io[6],Location,PIN_B16,Yes,,,
Ok,,PMOD_io[7],Location,PIN_C16,Yes,,,
Ok,,USR_AIN_io[0],Location,PIN_T12,Yes,,,
Ok,,USR_AIN_io[1],Location,PIN_R11,Yes,,,
Ok,,UART_BDBUS_io[0],Location,PIN_R7,Yes,,,
Ok,,UART_BDBUS_io[1],Location,PIN_T7,Yes,,,
Ok,,UART_BDBUS_io[2],Location,PIN_R6,Yes,,,
Ok,,UART_BDBUS_io[3],Location,PIN_T6,Yes,,,
Ok,,UART_BDBUS_io[4],Location,PIN_R5,Yes,,,
Ok,,UART_BDBUS_io[5],Location,PIN_T5,Yes,,,
Ok,,UART_BDBUS_io,I/O Standard,3.3-V LVTTL,Yes,cyc1000_top,,
Ok,,USER_BTN_i,I/O Standard,3.3-V LVTTL,Yes,cyc1000_top,,
Ok,,LED_o,I/O Standard,3.3-V LVTTL,Yes,cyc1000_top,,
Ok,,USR_AIN_io,I/O Standard,3.3-V LVTTL,Yes,cyc1000_top,,
Ok,,PMOD_io,I/O Standard,3.3-V LVTTL,Yes,cyc1000_top,,
Ok,,MKR_*,I/O Standard,3.3-V LVTTL,Yes,cyc1000_top,,
Ok,,SEN_*,I/O Standard,3.3-V LVTTL,Yes,cyc1000_top,,
Ok,,SDRAM_*,I/O Standard,3.3-V LVTTL,Yes,cyc1000_top,,
Ok,,CLK*,I/O Standard,3.3-V LVTTL,Yes,cyc1000_top,,
,<<new>>,<<new>>,<<new>>,,,,,
------------------------------------------------------------------------------
--
-- file cyc1000_top.vhd
-- author Peter Bartmann <peter.bartmann@th-luebeck.de>
-- data 2021-03-19
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_bit.all;
entity cyc1000_top is
port(
-- Clock
CLK12M_i : in std_logic; -- (U7) external clock tree: shared with FT2232H (U3)
CLKx_i : in std_logic; -- (U6) optional oscillator
-- SDRAM
SDRAM_CLK_o : out std_logic;
SDRAM_CKE_o : out std_logic; -- clock enable
SDRAM_nCS_o : out std_logic; -- chip select
SDRAM_nRAS_o : out std_logic; -- row address strobe
SDRAM_nCAS_o : out std_logic; -- column address strobe
SDRAM_nWE_o : out std_logic; -- write enable
SDRAM_ADDR_o : out std_logic_vector(13 downto 0);
SDRAM_BA_o : out std_logic_vector( 1 downto 0);
SDRAM_DQ_io : inout std_logic_vector(15 downto 0);
SDRAM_DQM_o : out std_logic_vector( 1 downto 0);
-- accelerometer connections
SEN_INT_i : in std_logic_vector(1 downto 0);
SEN_SDI_o : out std_logic; -- SPI MOSI
SEN_SDO_i : in std_logic; -- SPI MISO
SEN_SPC_o : out std_logic; -- SPI clock
SEN_CS_o : out std_logic; -- SPI chip select
-- arduino MKR connectors
MKR_AREF_io : inout std_logic;
MKR_AIN_io : inout std_logic_vector( 6 downto 0);
MKR_D_io : inout std_logic_vector(14 downto 0);
MKR_D_R_io : inout std_logic_vector(12 downto 11); -- shared with D_io(12 downto 11) but with resistor
-- PMOD connector
PMOD_io : inout std_logic_vector(7 downto 0);
-- additional user io
USR_AIN_io : inout std_logic_vector(1 downto 0);
-- UART with FT2232H (U3)
UART_BDBUS_io : inout std_logic_vector(5 downto 0);
-- push buttons
USER_BTN_i : in std_logic;
-- LEDs
LED_o : out std_logic_vector(7 downto 0)
);
end entity cyc1000_top;
architecture rtl of cyc1000_top is
begin
end;
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment